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Cortex-X5 (Chaberton-ELP) µarch
General Info
Arch Type	CPU
Designer	ARM Holdings
Manufacturer	TSMC
Introduction	2024
Phase-out	Cancelled
Cores
Core Names	Cortex-X5
Succession
Cortex-X3 (Makalu-ELP) Cortex-X4 (Hunter-ELP) Cortex-X925 (Blackhawk) Cortex-X930 (Travis)
Contemporary
Cortex-A725 (Chaberton) Cortex-A730 (Gelas)

Cortex-X5 (Chaberton-ELP) is the successor to the Cortex-X4 (Hunter-ELP), a performance-enhanced version of the
Cortex-A725 (Chaberton), low-power high-performance ARM microarchitecture designed by Arm for the mobile market.

Cortex-X925

Cortex-X925 (Blackhawk) is the successor to the Cortex-X4 (Hunter-ELP), a performance-enhanced version of the
Cortex-A725 (Chaberton), low-power high-performance ARM microarchitecture designed by Arm for the mobile market.

Cortex-X

ARM • Cortex

Year	Cortex-X Core	Cortex-A Core
2020	Cortex-X1 (Hera) Cortex-X1C (Hera-C)	Cortex-A78 (Hercules) Cortex-A78C (Hera Prime)
2021	Cortex-X2 (Matterhorn-ELP)	Cortex-A710 (Matterhorn) Cortex-A510 (Klein)
2022	Cortex-X3 (Makalu-ELP)	Cortex-A715 (Makalu)
2023	Cortex-X4 (Hunter-ELP)	Cortex-A720 (Hunter) Cortex-A520 (Hayes)
2024	Cortex-X5 (Chaberton-ELP) Cortex-X925 (Blackhawk)	Cortex-A720AE (Hunter-AE) Cortex-A725 (Chaberton)
2025	Cortex-X930 (Travis)	Cortex-A730 (Gelas) Cortex-A530 (Nevis)

Architecture

Cortex-X925 is a high-performance CPU core designed by Arm and introduced in 2024. It is part of the second-generation ARMv9.2 architecture and is built on a 3 nm process node. The Cortex-X925 is designed to excel in single-threaded instruction per clock (IPC) performance, making it ideal for high-performance mobile computing.

The Cortex-X925 is designed to be used in both homogeneous and heterogeneous DynamIQ clusters, providing flexibility in various system configurations.

Key features

• Support for ARMv9.2-A instruction set: the core supports A64 instruction set and AArch64 execution state at all exception levels.
• 10-wide decode and dispatch width: this allows the core to process more instructions per cycle, increasing overall throughput.
• Increased L1 instruction cache (I$) bandwidth: the core features a 2x increase in L1 I$ bandwidth, ensuring quick instruction fetch and decode.
• Enhanced branch prediction unit: techniques such as folded-out unconditional direct branches reduce mispredicted branches, leading

to fewer pipeline flushes and higher sustained IPC.

• Doubled instruction window size: this reduces stalls and improves the efficiency of the execution pipeline.
• Scalable Vector Extension (SVE) and SVE2: these extensions provide advanced SIMD and floating-point support.
• Error protection: the core includes error protection on L1 instruction and data caches, L2 cache,

and MMU Translation Cache (MMU TC) with parity or ECC.

Comparison

"Prime" core

Architecture	Cortex-A78	Cortex-X1	Cortex-X2	Cortex-X3	Cortex-X4	Cortex-X925	Cortex-X930
Code name	Hercules	Hera	Matterhorn-ELP	Makalu-ELP	Hunter-ELP	Blackhawk	Travis
ISA	ARMv8.2-A		ARMv9.0-A		ARMv9.2-A
Peak clock speed	~3.0 GHz			~3.3 GHz	~3.4 GHz	~3.8 GHz	~4.2 GHz
Max in-flight	2x 160	2x 224	2x 288	2x 320	2x 384	2x 768
L0 (Mops entries)	1536	3072		1536	0
L1-I + L1-D	32+32 KiB	64+64 KiB		64+64 KiB		64+64 KiB
L2	128–512 KiB	0.25–1 MiB			0.5–2 MiB	2–3 MiB
L3	0–8 MiB		0–16 MiB		0–32 MiB
Decode width	4	5		6	10	10
Dispatch	6/cycle	8/cycle			10/cycle